System on chip FPGA designs of a parameterized particle image velocimetry algorithm

Abstract : In this paper, an efficient architecture for Particle Image Velocimetry algorithm is proposed. The aim of this work is the design of a system of chip FPGA that can be adapted to application characteristics (size of image, pixel clock frequency...). From these specifications, the designer defines the suitable number of processing modules. Required resources and execution time can also be predicted before the implementation process that makes the design flow faster and more secure.
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Conference papers
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https://hal-ujm.archives-ouvertes.fr/ujm-00142044
Contributor : Virginie Fresse <>
Submitted on : Tuesday, April 17, 2007 - 10:57:16 AM
Last modification on : Wednesday, July 25, 2018 - 2:05:30 PM

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  • HAL Id : ujm-00142044, version 1

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Virginie Fresse, Nathalie Bochard, Alain Aubert. System on chip FPGA designs of a parameterized particle image velocimetry algorithm. IEEE International Symposium on Circuits and Systems, May 2006, Kos, Greece. 4 p. ⟨ujm-00142044⟩

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