Hardware platform for testing performance of TRNGs embedded in Actel fusion FPGA

Michal Varchola (1) , Milos Drutarovsky (1) , Robert Fouquet (2) , Viktor Fischer (2)

1 Department of Electronics and Multimedia Communications
2 LHC - Laboratoire Hubert Curien

The paper presents hardware SoPC platform for testing performance of various TRNGs embedded in Actel FPGAs. The SoPC was implemented in the recent Actel Fusion ARM enabled FPGA device. It consists of four main blocks - CoreMP7 (Actel's soft-core industry standard ARM7 processor) for managing the SoPC, SRAM and Flash memories embedded inside the FPGA for storage and execution of CoreMP7 embedded software, custom TRNG design and Hi-Speed USB 2.0 interface based on a Cypress USB microcontroller for fast download of generated data to the computer. TRNG and USB interface peripherals are directly connected to the CoreMP7 peripheral bus to improve flexibility of using it. The results of NIST statistical testing of experimental PLL-based TRNG implementation demonstrate potential of designed hardware platform as well as new feature of Actel Fusion FPGAs - internal RC oscillator that could enhance security of the implemented TRNGs.

Keywords: Actel Fusion; USB interface.; True random number generator; PLL; statistical tests; NIST; ARM7; USB interface

Domains: Embedded Systems; Electronics; Cryptography and Security [cs.CR]

Michal Varchola, Milos Drutarovsky, Robert Fouquet, Viktor Fischer. Hardware platform for testing performance of TRNGs embedded in Actel fusion FPGA. Radioelektronika 2008, Apr 2008, Prague, Czech Republic. pp.145-148. ⟨ujm-00305499⟩