Model of a True Random Number Generator Aimed at Cryptographic Applications

Martin Šimka 1 Viktor Fischer 2 Milos Drutarovský 1 Jacques Fayolle 3
1 Department of Electronics and Multimedia Communications
2 LHC - Laboratoire Hubert Curien [Saint Etienne]
3 DIOM - Dispositifs et Instrumentation en Optoélectronique et micro-ondes
Abstract : The paper presents a simple stochastic model of a True Random Number Generator, which extracts randomness from the tracking jitter of a phase-locked loop. The existence of such a model is a necessary condition in the security certification process. The proposed model can be used to test, in real time, the proper behavior of the generator and thus to guarantee its robustness against cryptographic attacks. The model is validated on real data, which have been obtained using Altera Stratix Nios and Altera Stratix DSP Professional boards.
keyword : VHDL. True random number generator FPGAs PLL Jitter VHDL
Document type :
Conference papers
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https://hal-ujm.archives-ouvertes.fr/ujm-00307647
Contributor : Viktor Fischer <>
Submitted on : Tuesday, July 29, 2008 - 12:16:51 PM
Last modification on : Wednesday, July 25, 2018 - 2:05:30 PM

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  • HAL Id : ujm-00307647, version 1

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UNIV-ST-ETIENNE | CNRS | LAHC | IOGS | PARISTECH

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Martin Šimka, Viktor Fischer, Milos Drutarovský, Jacques Fayolle. Model of a True Random Number Generator Aimed at Cryptographic Applications. IEEE International Symposium on Circuits and Systems – ISCAS, May 2006, Kos, Greece. pp.5619-5622. ⟨ujm-00307647⟩

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