Embedded testing of the source of randomness in FPGAs - Clock jitter evaluation and measurements

Abstract : True random number generators in Field Programmable Gate Arrays (FPGAs) use mostly a short-term variation of an event from its ideal position in time (a jitter) to generate random numbers. In this presentation, we analyze the clock jitter as a source of randomness. Starting from this analysis, we present basic kinds of jitter that are employed in existing generators. In order to secure the generators, we propose two methods of embedded jitter measurements: one aimed for RO-based TRNGs and the other one for PLL-based TRNGs. Both methods are simple to implement in FPGAs and they can be used to test the quality of the source of randomness in real time.
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https://hal-ujm.archives-ouvertes.fr/ujm-00368675
Contributor : Viktor Fischer <>
Submitted on : Tuesday, March 17, 2009 - 11:17:07 AM
Last modification on : Wednesday, July 25, 2018 - 2:05:31 PM

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  • HAL Id : ujm-00368675, version 1

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Viktor Fischer, Florent Bernard, Alain Aubert. Embedded testing of the source of randomness in FPGAs - Clock jitter evaluation and measurements. cryptarchi 2008, Jun 2008, Trégastel, France. ⟨ujm-00368675⟩

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