Modeling and securing RO-based TRNG in FPGAs - Jitter accumulation from local and global sources
Abstract
Many true random number generators in Field Programmable Gate Arrays (FPGAs) employ the timing jitter from ring oscillator clocks as a source of randomness. In this presentation we are focusing on the jitter generated in ring oscillators. We use a simple physical model of jitter sources to show that the random jitter accumulates slower than the global and manipulable deterministic jitter. This fact, which can be used to attack generators, is not considered even in most recent designs considered to be secure. We propose simple but efficient countermeasure against these attacks. The method is validated using the proposed behavioral VHDL model and it is shown to be efficient in hardware, too.