Secured Reconfigurable Cryptographic Processor

Abstract : This work presents reconfigurable processor aimed at symmetric-key cryptographic applications with architecture dedicated to the common cryptography tasks: 128-bit separated data and key registers, dedicated instruction set optimized for key generation and management, embedded cipher, etc. From the architecture point of view, the most important is the physical separation of data and key registers and buses, insuring that the confidential keys will never leave the system in clear. This way, the processor enables to separate red and black security zones easily. What is more, the goal is to achieve complete physical isolation of key management and data zones inside the single FPGA (required for security levels 3 and 4 as defined in FIPS-140-2 ).
Type de document :
Communication dans un congrès
PAca Security Trends In embedded Systems Workshop, PASTIS, Jun 2010, Gardanne, France. pp.NN, 2010
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https://hal-ujm.archives-ouvertes.fr/ujm-00533246
Contributeur : Nathalie Bochard <>
Soumis le : vendredi 5 novembre 2010 - 15:20:39
Dernière modification le : jeudi 11 janvier 2018 - 06:20:35

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  • HAL Id : ujm-00533246, version 1

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Lubos Gaspar, Viktor Fischer, Florent Bernard. Secured Reconfigurable Cryptographic Processor. PAca Security Trends In embedded Systems Workshop, PASTIS, Jun 2010, Gardanne, France. pp.NN, 2010. 〈ujm-00533246〉

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