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Secured Reconfigurable Cryptographic Processor

Abstract : This work presents reconfigurable processor aimed at symmetric-key cryptographic applications with architecture dedicated to the common cryptography tasks: 128-bit separated data and key registers, dedicated instruction set optimized for key generation and management, embedded cipher, etc. From the architecture point of view, the most important is the physical separation of data and key registers and buses, insuring that the confidential keys will never leave the system in clear. This way, the processor enables to separate red and black security zones easily. What is more, the goal is to achieve complete physical isolation of key management and data zones inside the single FPGA (required for security levels 3 and 4 as defined in FIPS-140-2 ).
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Contributor : Nathalie Bochard Connect in order to contact the contributor
Submitted on : Friday, November 5, 2010 - 3:20:39 PM
Last modification on : Saturday, June 25, 2022 - 7:25:40 PM


  • HAL Id : ujm-00533246, version 1



Lubos Gaspar, Viktor Fischer, Florent Bernard. Secured Reconfigurable Cryptographic Processor. PAca Security Trends In embedded Systems Workshop, PASTIS, Jun 2010, Gardanne, France. pp.NN. ⟨ujm-00533246⟩



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