A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

Michael Grand (1) , Lilian Bossuet (2) , Bertrand Le Gal (1) , Dominique Dallet (1) , Guy Gogniat (3)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 LHC - Laboratoire Hubert Curien [Saint Etienne]
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)

This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors.

Domains: Computer Science [cs]; Embedded Systems; Computer Science [cs]; Cryptography and Security [cs.CR]

Michael Grand, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet, Guy Gogniat. A Multi-Core AES Cryptoprocessor for Multi-Channel SDR. Military Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7. ⟨ujm-00552208⟩