A Multi-Core AES Cryptoprocessor for Multi-Channel SDR - Archive ouverte HAL Access content directly
Conference Papers Year : 2010

A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

(1) , (2) , (1) , (1) , (3)
1
2
3

Abstract

This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors.
Not file

Dates and versions

ujm-00552208 , version 1 (05-01-2011)

Identifiers

  • HAL Id : ujm-00552208 , version 1

Cite

Michael Grand, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet, Guy Gogniat. A Multi-Core AES Cryptoprocessor for Multi-Channel SDR. Military Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7. ⟨ujm-00552208⟩
463 View
0 Download

Share

Gmail Facebook Twitter LinkedIn More