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A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

Michael Grand 1 Lilian Bossuet 2 Bertrand Le Gal 1 Dominique Dallet 1 Guy Gogniat 3
1 IMS - Laboratoire de l'intégration, du matériau au système
2 LHC - Laboratoire Hubert Curien [Saint Etienne]
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
Abstract : This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors.
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Conference papers
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https://hal-ujm.archives-ouvertes.fr/ujm-00552208
Contributor : Lilian Bossuet <>
Submitted on : Wednesday, January 5, 2011 - 4:42:35 PM
Last modification on : Monday, May 17, 2021 - 11:24:01 AM

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  • HAL Id : ujm-00552208, version 1

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UNIV-ST-ETIENNE | INSTITUT-TELECOM | CNRS | IMS-BORDEAUX | UNIV-BREST | LAHC | IMS-BORDEAUX-FUSION | LAB-STICC | IOGS | PARISTECH | UDL

Citation

Michael Grand, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet, Guy Gogniat. A Multi-Core AES Cryptoprocessor for Multi-Channel SDR. Military Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7. ⟨ujm-00552208⟩

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