A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

Abstract : This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors.
Type de document :
Communication dans un congrès
Military Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7, 2010
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https://hal-ujm.archives-ouvertes.fr/ujm-00552208
Contributeur : Lilian Bossuet <>
Soumis le : mercredi 5 janvier 2011 - 16:42:35
Dernière modification le : jeudi 8 novembre 2018 - 13:50:03

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  • HAL Id : ujm-00552208, version 1

Citation

Michael Grand, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet, Guy Gogniat. A Multi-Core AES Cryptoprocessor for Multi-Channel SDR. Military Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7, 2010. 〈ujm-00552208〉

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