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A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

Abstract : This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors.
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Contributor : Lilian Bossuet Connect in order to contact the contributor
Submitted on : Wednesday, January 5, 2011 - 4:42:35 PM
Last modification on : Saturday, June 25, 2022 - 7:25:42 PM


  • HAL Id : ujm-00552208, version 1


Michael Grand, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet, Guy Gogniat. A Multi-Core AES Cryptoprocessor for Multi-Channel SDR. Military Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7. ⟨ujm-00552208⟩



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