Generation of emulation platforms for NoC exploration on FPGA

Abstract : NoC (Network on Chip) architecture exploration is an up to date problem with today's multimedia applications and platforms. The presented methodology gives a solution to easily evaluate timing and resource performances tuning several architectural parameters, in order to find the appropriate NoC architecture with a unique emulation platform. In this paper, a design flow that generates NoC-based emulation platforms on FPGA is presented. From specified traffic scenarios, our tool automatically inserts appropriate IP blocks (emulation blocks and routing algorithm) and generates an RTL NoC model with specific and tunable components that is synthesized on FPGA.
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Communication dans un congrès
IEEE Symposium on Rapid System Prototyping, May 2011, Karlsruhe, Germany. 8 p., 2011
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https://hal-ujm.archives-ouvertes.fr/ujm-00598751
Contributeur : Virginie Fresse <>
Soumis le : mardi 7 juin 2011 - 14:46:56
Dernière modification le : mercredi 16 mai 2018 - 18:30:04

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  • HAL Id : ujm-00598751, version 1

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Junyan Tan, Virginie Fresse, Frederic Rousseau. Generation of emulation platforms for NoC exploration on FPGA. IEEE Symposium on Rapid System Prototyping, May 2011, Karlsruhe, Germany. 8 p., 2011. 〈ujm-00598751〉

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