A scalable end effective routing algorithm for multi-FPGA based large scale NoC

Zhiwei Ge (1) , Junyan Tan (2) , Virginie Fresse (2) , Frédéric Rousseau (3) , Sunying Yao (1)

1 ASIC Design Center - ASIC Design Center
2 LHC - Laboratoire Hubert Curien
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

In the context of the FPGA resource limitation for large scale NoC, multi-FPGA based solutions are proposed. Due to the scalable routing scheme and packet format, the proposed routing algorithm can be used with both intra-FPGA and inter-FPGA communications. The effectiveness of the scheme is that it can be used for any multi-FPGA based NoC with small amount extra resource consumption.

Domains: Embedded Systems

Zhiwei Ge, Junyan Tan, Virginie Fresse, Frédéric Rousseau, Sunying Yao. A scalable end effective routing algorithm for multi-FPGA based large scale NoC. COLLOQUE NATIONAL DU GDR SOC-SIP, Jun 2011, Lyon, France. 2 p. ⟨ujm-00601664⟩