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generation of hardware emulation platforme for multi-FPGA based NoC

Zhiwei Ge 1 Junyan Tan 2 Virginie Fresse 2 Frederic Rousseau 3 Sunying Yao 1
1 ASIC Design Center - ASIC Design Center
2 LHC - Laboratoire Hubert Curien [Saint Etienne]
3 TIMA [2007-2015] - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés [2007-2015]
Abstract : Multi-FPGA based emulation platform for NoC (Network-on-Chip) gives a solution to the resource limitation of single FPGA based emulation platform. The generic design flow is needed to generate the emulation architecture for multi-FPGA based NoC.We propose a design flow that generates multi-FPGA based NoC. With the routing IP library for multi-FPGA based 3D NoC, the platform specification, the data transfer specification and emulation blocks, the generation tools can automatically generates a hardware emulation platform for multi-FPGA based NoC.
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Conference papers
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https://hal-ujm.archives-ouvertes.fr/ujm-00634884
Contributor : Virginie Fresse <>
Submitted on : Monday, October 24, 2011 - 11:25:54 AM
Last modification on : Tuesday, September 15, 2020 - 4:40:10 PM

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  • HAL Id : ujm-00634884, version 1

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UNIV-ST-ETIENNE | CNRS | TIMA | LAHC | UGA | IOGS | PARISTECH | UDL

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Zhiwei Ge, Junyan Tan, Virginie Fresse, Frederic Rousseau, Sunying Yao. generation of hardware emulation platforme for multi-FPGA based NoC. Journées scientifiques 2011 du projet SEmba, Oct 2011, Valence, France. ⟨ujm-00634884⟩

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