Abstract : Multi-FPGA based emulation platform for NoC (Network-on-Chip) gives a solution to the resource limitation of single FPGA based emulation platform. The generic design flow is needed to generate the emulation architecture for multi-FPGA based NoC.We propose a design flow that generates multi-FPGA based NoC. With the routing IP library for multi-FPGA based 3D NoC, the platform specification, the data transfer specification and emulation blocks, the generation tools can automatically generates a hardware emulation platform for multi-FPGA based NoC.
https://hal-ujm.archives-ouvertes.fr/ujm-00634884
Contributor : Virginie Fresse
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Submitted on : Monday, October 24, 2011 - 11:25:54 AM
Last modification on : Wednesday, July 25, 2018 - 2:05:30 PM
Zhiwei Ge, Junyan Tan, Virginie Fresse, Frederic Rousseau, Sunying Yao. generation of hardware emulation platforme for multi-FPGA based NoC. Journées scientifiques 2011 du projet SEmba, Oct 2011, Valence, France. ⟨ujm-00634884⟩
