Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs

Abdelkarim Cherkaoui (1) , Viktor Fischer (1) , Alain Aubert (1) , Laurent Fesquet (2)

1 LHC - Laboratoire Hubert Curien
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where sources of randomness are very limited. Inverter Ring Oscillators (IRO) are relatively well characterized as entropy sources. However, it is known that they are very sensitive to working conditions. This fact makes them vulnerable to attacks. On the other hand, Self-Timed Rings (STR) are currently considered as a promising solution to generate robust clock signals. Although many studies deal with their temporal behavior and robustness in Application Specific Integrated Circuits (ASIC), equivalent study does not exist for FPGAs. Furthermore, these oscillators were not analyzed and characterized as entropy sources aimed at TRNG design. In this paper, we analyze STRs as entropy sources for TRNGs implemented in FPGAs. Next, we compare STRs and IROs when serving as sources of randomness. We show that STRs represent very interesting alternative to IROs: they are more robust to environmental fluctuations and they exhibit lower extra-device frequency variations.

Keywords: True Random Numbers Generators (TRNG); oscillators; Self-Timed Rings (STR); jitter

Domains: Computer Science [cs]; Embedded Systems; Computer Science [cs]; Cryptography and Security [cs.CR]

Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet. Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs. Design Automation and Test in Europe (DATE 2012), Mar 2012, Dresden, Germany. pp.1-6. ⟨ujm-00667639⟩