On the way to secure random number generation

Abstract : Physical True Random Number Generator (P-TRNG) is a cryptographic primitive based on physical noisy phenomena. A flaw in security of the P-TRNG will directly impact the security of the whole cryptographic system. The vulnerability of the P-TRNG to non-invasive attacks has been recently highlighted. Thus, their designer should take into account such a vulnerability in order to increase the robustness of the generators against attacks. Nowadays, the security of the P-TRNG is based on an on-line execution of simple tests of the source of randomness, adapted to the structure of the generator, which ensure that the randomness of the generated sequence is due to the desired noisy physical phenomenon and that it is not manipulated. We will present a methodology for designing these tests that can be easily embeddable in logic devices. This methodology is based on a keen understanding of random and pseudo-random mechanisms that occur in the generator. In this way, by combining the models of each of these mechanisms, we propose a stochastic description of the generated random bit stream. In the case of the P-TRNG implemented in digital devices, our approach is translated into 3 levels of modeling. The low level consist in a description of all electronic noises present in transistors. The middle level models the conversion process, which transforms noises provided by transistors into a raw binary signal. The top level model deals with the sampling mechanisms of this raw random bit stream. This way, by combining and correctly linking these models we describe mathematically the raw random sequence generation. This description is than used for designing adapted embedded tests as required by the recent AIS 31 recommendations. In order to validate the approach, we applied the proposed methodology to the design of a secured phase-locked loop based true random number generator. In this case, the models at different levels have to take into account the physical characteristics of the underlying technology, source of randomness exploited (e.g. the noise in the voltage control oscillator) and the way this randomness is extracted (sampling of the generated jittery signal by a reference clock in a flip-flop).
Type de document :
Communication dans un congrès
Constructive Side-channel Analysis and Secure Design conference, COSADE 2013, Mar 2013, paris, France. pp.1, 2013
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https://hal-ujm.archives-ouvertes.fr/ujm-00833914
Contributeur : Nathalie Bochard <>
Soumis le : jeudi 13 juin 2013 - 16:56:45
Dernière modification le : jeudi 11 janvier 2018 - 06:20:35

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  • HAL Id : ujm-00833914, version 1

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Patrick Haddad, Florent Bernard, Viktor Fischer. On the way to secure random number generation. Constructive Side-channel Analysis and Secure Design conference, COSADE 2013, Mar 2013, paris, France. pp.1, 2013. 〈ujm-00833914〉

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