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True Random Numbers Generation Using Asynchronous Circuits

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Abstract

The proposed true random number generator (TRNG) exploits the jitter of events propagating in a self-timed ring (STR) for generating random bit sequences at a very high bit rate. It takes advantage from a special feature of STRs allowing to adjust the time elapsed between successive events as short as needed, even in order of picoseconds. If the time interval between the events is set in concordance with the clock jitter magnitude, a simple entropy extraction scheme can be applied for generating random numbers. The proposed STR-based TRNG (STRNG) follows AIS31 recommendations: by using the proposed stochastic model, the designer can compute the lower entropy bound as a function of the STR characteristics (number of stages, oscillation period and jitter magnitude). Using the obtained entropy assessment, he can then set up the compression rate in the arithmetic post-processing block in order to reach the required security level determined by the entropy per output bit. Implementations of the generator in two FPGA families illustrate its feasibility in digital technologies and conrm that it can provide high quality random bit sequences letting pass the statistical tests required by AIS31 at rates as high as 200 Mbit/s.
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Dates and versions

ujm-00840445 , version 1 (02-07-2013)

Identifiers

  • HAL Id : ujm-00840445 , version 1

Cite

Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet. True Random Numbers Generation Using Asynchronous Circuits. Journées scientifiques SEmba 2013, May 2013, St Germain au Mont d'Or, France. ⟨ujm-00840445⟩
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