Evaluation of Delay PUFs on CMOS 65 nm Technology: ASIC vs FPGA

Zouha Cherif; Jean-Luc Danger; Lilian Bossuet

Evaluation of Delay PUFs on CMOS 65 nm Technology: ASIC vs FPGA

Zouha Cherif ^{1, 2} Jean-Luc Danger ² Lilian Bossuet ¹

1 LHC - Laboratoire Hubert Curien [Saint Etienne]

Abstract : This work presents a comparison between the performance of two types of silicon Physically Unclonable Functions (PUFs), namely the arbiter and the loop PUFs. The arbiter and the loop PUF are designed on two CMOS-65nm technology platforms: ASIC and FPGA (Xilinx Virtex-5). A mixed PUF design is proposed to allow a fair comparison between the two structures. The principal of the mixed PUF design consists on the use of the same delay chains on both arbiter and loop PUF structures. The comparison analysis reveals that the arbiter PUF structure has the worst performance when compared to the loop PUF, on both platforms. We also observe that the performance for both structures are better when designed on ASIC.

Document type :

Conference papers

Domain :

Computer Science [cs] / Embedded Systems

Computer Science [cs] / Cryptography and Security [cs.CR]

Complete list of metadatas

https://hal-ujm.archives-ouvertes.fr/ujm-00840962
Contributor : Nathalie Bochard <>
Submitted on : Wednesday, July 3, 2013 - 3:44:40 PM
Last modification on : Wednesday, June 5, 2019 - 5:22:05 PM

Evaluation of Delay PUFs on CMOS 65 nm Technology: ASIC vs FPGA

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Evaluation of Delay PUFs on CMOS 65 nm Technology: ASIC vs FPGA

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