Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

M. Gaillardin 1 Sylvain Girard 2 Philippe Paillet 1 Jean-Luc Leray 1 V. Goiffon 3 P. Magnan 3 Claude Marcandella 1 M. Martinez 1 Melanie Raine 1 O. Duhamel 1 N. Richard 1 F. Andrieu 4 S. Barraud 4 O. Faynot 4
1 DAM/DIF - DAM Île-de-France
2 LHC - Laboratoire Hubert Curien [Saint Etienne]
3 ISAE-SUPAERO - Institut Supérieur de l'Aéronautique et de l'Espace
4 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
Abstract : This paper investigates the TID sensitivity of silicon-based technologies at several MGy irradiation doses to evaluate their potential for high TID-hardened circuits. Such circuits will be used in several specific applications suc as safety systems of current or future nuclear power plants considering various radiation environments including normal and accidental operating conditions, high energy physics instruments, fusion experiments or deep space missions. Various device designs implemented in well established bulk silicon and Partially Depleted SOI technologies are studied here up to 3 MGy. Furthermore, new insights are given on the vulnerability of more advanced technologies including planar Fully Depleted SOI and multiple-gate SOI transistors at such high dose. Potential of tested technologies are compared and discussed for stand-alone integrated circuits.
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Article dans une revue
IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2013, 60 (4), pp.2590 - 2597. 〈10.1109/TNS.2013.2249095〉
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https://hal-ujm.archives-ouvertes.fr/ujm-00854044
Contributeur : Sylvain Girard <>
Soumis le : lundi 26 août 2013 - 10:55:00
Dernière modification le : jeudi 29 mars 2018 - 09:04:04

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UNIV-ST-ETIENNE | CEA | LAHC | DRT | LETI

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M. Gaillardin, Sylvain Girard, Philippe Paillet, Jean-Luc Leray, V. Goiffon, et al.. Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2013, 60 (4), pp.2590 - 2597. 〈10.1109/TNS.2013.2249095〉. 〈ujm-00854044〉

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