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Conference Papers Lecture Notes in Computer Science Year : 2013

A Very High Speed True Random Number Generator with Entropy Assessment

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Abstract

The proposed true random number generator (TRNG) exploits the jitter of events propagating in a self-timed ring (STR) to generate random bit sequences at a very high bit rate. It takes advantage of a special feature of STRs that allows the time elapsed between successive events to be set as short as needed, even in the order of picoseconds. If the time interval between the events is set in concordance with the clock jitter magnitude, a simple entropy extraction scheme can be applied to generate random numbers. The proposed STR-based TRNG (STRNG) follows AIS31 recommendations: by using the proposed stochastic model, designers can compute a lower entropy bound as a function of the STR characteristics (number of stages, oscillation period and jitter magnitude). Using the resulting entropy assessment, they can then set the compression rate in the arithmetic post-processing block to reach the required security level determined by the entropy per output bit. Implementation of the generator in two FPGA families confirmed its feasibility in digital technologies and also confirmed it can provide high quality random bit sequences that pass the statistical tests required by AIS31 at rates as high as 200 Mbit/s.
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Dates and versions

ujm-00859906 , version 1 (10-09-2013)

Identifiers

  • HAL Id : ujm-00859906 , version 1

Cite

Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert. A Very High Speed True Random Number Generator with Entropy Assessment. Cryptographic Hardware and Embedded Systems -- CHES 2013 15th International Workshop on Cryptographic Hardware and Embedded Systems -- CHES 2013, Aug 2013, Santa Barbara, California, United States. pp.179-196. ⟨ujm-00859906⟩
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