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Verification of IP Watermark using Correlation Analysis

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Abstract

The increasing production costs of electronic devices and changes in the design methods of integrated circuits (ICs) has led to emerging threats in the microelectronics industry. Today, high value chips are the target of counterfeiting, theft and malicious hardware insertion (such as hardware trojans). Intellectual property (IP) protection has become a major concern and we propose to fight counterfeiting and theft by designing salutary hardware (salware). Instead of insert malicious effects inside an IP like a malware (e.g. a hardware trojan), a salware uses the same techniques, strategies and means for IP protection. One of the most studied salware is IP watermarking. Many works propose to target the finite state machine of digital IP to perform the atermarking. But, most of the time, the verification of the watermark is not clearly described. This conduces to a lack of credibility of these works. This paper proposes a watermark verification scheme using a correlation analysis based on the measurement of the IC power consumption. This article presents this process of verification and also discusses the selection of its parameters according to experimental results.
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Dates and versions

ujm-01011317 , version 1 (23-06-2014)

Identifiers

  • HAL Id : ujm-01011317 , version 1

Cite

Cédric Marchand, Lilian Bossuet, Edward Jung. Verification of IP Watermark using Correlation Analysis. International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices (Cryptarchi 2014), Jun 2014, Annecy, France. pp.13. ⟨ujm-01011317⟩
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