D. A. Hodges, Building the fabless/foundry business model, IEEE Solid-State Circuits Magazine, issue.34, pp.7-44, 2011.

C. Gorman, Counterfeit chips on the rise, IEEE Spectrum, vol.49, issue.6, pp.49-65, 2012.
DOI : 10.1109/MSPEC.2012.6203952

M. Pecht and S. Tiku, Bogus!, IEEE Spectrum, vol.43, issue.5, pp.43-80, 2006.
DOI : 10.1109/MSPEC.2006.1628506

K. Huang, J. Guo, and Z. Xu, Recycling of waste printed circuit boards: A review of current technologies and treatment status in China, Journal of Hazardous Materials, vol.164, issue.2-3, pp.399-408, 2009.
DOI : 10.1016/j.jhazmat.2008.08.051

I. Mcloughlin, Reverse engineering of embedded consumer electronic systems, 2011 IEEE 15th International Symposium on Consumer Electronics (ISCE), pp.352-356, 2011.
DOI : 10.1109/ISCE.2011.5973848

G. Masalskis and R. Navickas, Reverse engineering of CMOS integrated circuits', Elektronika ir Elektrotechnika -Electronics and Electrical Engineering, pp.28-31, 2008.

K. Nohl, D. Evans, S. Starbug, and H. Plotz, Reverse-engineering a cryptographic RFID tag, 17th Conference on Security symposium, pp.185-194, 2008.

M. Brutscheck, M. Franke, A. T. Schwarzbacher, and S. Becker, Non-invasive reverse engineering of CMOS integrated circuits, IEEE 17th Telecommunications Forum TELFOR, 2009.

M. Brutscheck, M. Franke, A. T. Schwarzbacher, and S. Becker, Investigation of finite state machines in unknown CMOS integrated circuits, 14th Electronic Devices and Systems IMAPS CS International Conference, pp.55-60, 2007.

S. Sood, D. Das, and M. Pecht, Screening for counterfeit electronic parts, Journal of Materials Science: Materials in Electronics, vol.7, issue.1, pp.22-1511, 2011.
DOI : 10.1007/s10854-011-0500-0

F. Koushanfar, S. Fazzari, and C. Mccants, Can EDA combat the rise of electronic counterfeiting?, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.133-138, 2012.
DOI : 10.1145/2228360.2228386

U. Guin, M. Tehranipoor, D. Dimase, and M. Megrdichian, Counterfeit IC detection and challenges ahead, ACM Special Interest Group on Design Automation, 2013.

J. Villasenor and M. Tehranipoor, The hidden dangers of chop-shop electronics, IEEE SPECTRUM, 2013.

J. A. Roy, F. Koushanfar, and I. Markov, EPIC, Proceedings of the conference on Design, automation and test in Europe, DATE '08, pp.1069-1074, 2008.
DOI : 10.1145/1403375.1403631

R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor, Trustworthy Hardware: Identifying and Classifying Hardware Trojans, Computer, vol.43, issue.10, pp.43-82, 2010.
DOI : 10.1109/MC.2010.299

M. Tehranipoor and F. Koushanfar, A survey of hardware trojan taxonomy and detection, IEEE Design & Test of Computers, issue.1, pp.27-37, 2010.

Y. Jin, N. Kupp, and Y. Makris, Experiences in hardware Trojan design and implementation', IEEE International Workshop on Hardware-Oriented Security and Trust, pp.50-57, 2009.

G. Hachez, A comparative study of software protection tools suited for e-commerce with contributions to software watermarking and smart cards, 2003.

Y. Alkabani and F. Koushanfar, Active hardware metering for intellectual property protection and security, USENIX Security Symposium, pp.291-306, 2007.

Y. Alkabani, F. Koushanfar, and M. Potkonjak, Remote activation of ICs for piracy prevention and digital right management, 2007 IEEE/ACM International Conference on Computer-Aided Design, pp.674-677, 2007.
DOI : 10.1109/ICCAD.2007.4397343

E. Jung, C. Hung, M. Yang, and S. Choi, An locking and unlocking primitive function of FSM-modeled sequential systems based on extracting logical property, International Journal of Information, issue.8, pp.16-6279, 2013.

J. A. Roy, F. Koushanfar, and I. Markov, Ending Piracy of Integrated Circuits, Computer, vol.43, issue.10, pp.43-73, 2010.
DOI : 10.1109/MC.2010.284

J. Rajendran, Y. Pinot, O. Sinanoglu, and R. Karri, Security analysis of logic obfuscation, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.83-89, 2012.
DOI : 10.1145/2228360.2228377

B. Liu and B. Wang, Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks, Europe Conference and Exhibition, pp.1-6, 2014.

A. Baumgarten, A. Tyagi, and J. Zambreno, Preventing IC Piracy Using Reconfigurable Logic Barriers, IEEE Design & Test of Computers, vol.27, issue.1, pp.27-66, 2010.
DOI : 10.1109/MDT.2010.24

A. Baumgarten, Preventing integrated circuit piracy using reconfigurable logic barriers', Master's thesis, 2010.

J. A. Roy, F. Koushanfar, and I. Markov, Protecting bus-based hardware IP by secret sharing, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.846-851, 2008.
DOI : 10.1145/1391469.1391684

A. Basak, Y. Zheng, and S. Bhunia, Active defense against counterfeiting attacks through robust antifusebased on-chip locks', 32nd IEEE VLSI Test Symposium, pp.1-6, 2014.

J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, Security analysis of integrated circuit camouflaging, Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security, CCS '13, pp.709-720
DOI : 10.1145/2508859.2516656

. Syphermedia, Circuit Camouflage Technology. SMI IP Protection and Anti-Tamper Technologies, 2012.

R. Imeson, A. Emtenan, S. Garg, and M. V. Tripunitara, Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation, 22nd USENIX Security Symposium, pp.495-510, 2013.

Y. Alkabani and F. Koushanfar, Active control and digital rights management of integrated circuit IP cores', International conference on Compilers, architectures and synthesis for embedded systems, pp.227-234, 2008.

W. Adi, B. Soudan, and N. Kassab, A protection mechanism for intellectual property rights (IPR) in FPGA design environment, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, pp.92-95, 2001.
DOI : 10.1109/ICECS.2003.1301984

J. Huang and J. Lach, IC activation and user authentication for security-sensitive systems', IEEE International workshop on Hardware-oriented security and trust, pp.76-80, 2008.

B. Badrignans, J. L. Danger, V. Fischer, G. Gogniat, and L. Torres, Security trends for FPGAs, 2011.
DOI : 10.1007/978-94-007-1338-3
URL : https://hal.archives-ouvertes.fr/lirmm-00616973

M. Tehranipoor and C. Wang, Introduction to FPGA security and trust, 2011.

A. S. Zeineddini and K. Gaj, Secure Partial Reconfiguration of FPGAs, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005., pp.155-162, 2005.
DOI : 10.1109/FPT.2005.1568540

J. Castillo, P. Huerta, V. Lopez, and J. I. Martinez, A secure self-reconfiguring architecture based on opensource hardware, Proc. Int. Conf. on Reconfigurable Computing and FPGAs, pp.7-10, 2005.

Y. Hori, A. Satoh, H. Sakane, and K. Toda, Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems, Proc. Int. Conf. on Field Programmable Logic and Applications, pp.23-28, 2008.
DOI : 10.1007/978-3-540-89598-5_18

S. Drimer and M. G. Kuhn, A Protocol for Secure Remote Updates of FPGA Configurations, Proc. Int'l Workshop on Reconfigurable Computing: Architectures, Tools and Applications, pp.50-61, 2009.
DOI : 10.1016/j.micpro.2006.02.001

J. Castillo, P. Huerta, and J. I. Martinez, Secure IP downloading for SRAM FPGAs', Microprocessors and Microsystems, pp.77-86, 2007.

A. Braeken, J. Genoe, S. Kubera, N. Mentens, A. Touhafi et al., Secure remote reconfiguration of an FPGA-based embedded system, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), pp.1-6, 2011.
DOI : 10.1109/ReCoSoC.2011.5981501

J. Vliegen, N. Mentens, and I. Verbauwhede, A single-chip solution for the secure remote configuration of FPGAs using bitstream compression, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013.
DOI : 10.1109/ReConFig.2013.6732330

A. Moradi, A. Barenghi, M. Kasper, and C. Paar, On the vulnerability of FPGA bitstream encryption against power analysis attacks, Proceedings of the 18th ACM conference on Computer and communications security, CCS '11, pp.111-124, 2011.
DOI : 10.1145/2046707.2046722

A. Moradi, M. Kasper, and C. Paar, Black-Box Side-Channel Attacks Highlight the Importance of Countermeasures ? An Analysis of the Xilinx Virtex-5 and Virtex-5 Bitstream Encryption Mechanism, Proc. Conf. on Topics in cryptology, pp.1-18, 2012.

A. Moradi, D. Oswald, C. Paar, and P. Swierczynski, Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II, Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '13, pp.91-100, 2013.
DOI : 10.1145/2435264.2435282

S. Skorobogatov and C. Woods, In the blink of an eye: There goes your AES key', Cryptology ePrint Archive, 2012.

A. T. Abdel-hamid, S. Tahar, and E. M. Aboulhamid, A survey on IP watermarking techniques', Design Automation for Embedded Systems, pp.211-227, 2004.

. Vsi-alliance, Intellectual property protection: schemes, alternatives and discussion', Intellectual Property Protection White Paper, Transactions on Signal Processing, issue.3, pp.48-854, 2000.

A. Rashid, J. Asher, W. H. Mangione-smith, and M. Potkonjak, Hierarchical watermarking for protection of DSP filter cores', IEEE Custom Integrated Circuits Conference, pp.39-42, 1999.

I. Torunoglu and E. Charbon, Watermarking-based copyright protection of sequential functions, IEEE Journal of Solid-State Circuits, issue.3, pp.35-434, 2000.

A. L. Oliveira, Techniques for the creation of digital watermarks in sequential circuit designs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.20, issue.9, pp.20-1101, 2011.
DOI : 10.1109/43.945306

D. Kirovski, Y. Hwang, M. Potkonjak, and J. Cong, Intellectual property protection by watermarking combinational logic synthesis solutions, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design , ICCAD '98, pp.194-198, 1998.
DOI : 10.1145/288548.288609

F. Koushanfar, I. Hong, and M. Potkonjak, Behavioral synthesis techniques for intellectual property protection, ACM Transactions on Design Automation of Electronic Systems, vol.10, issue.3, pp.10-523, 2005.
DOI : 10.1145/1080334.1080338

L. Gal, B. Bossuet, and L. , Automatic low-cost IP watermarking technique based on output mark insertions', Design Automation for Embedded Systems, pp.16-71, 2012.

M. Schmid, D. Ziener, and J. Teich, Netlist-level IP protection by watermarking for LUT-based FPGAs, 2008 International Conference on Field-Programmable Technology, pp.209-216, 2008.
DOI : 10.1109/FPT.2008.4762385

J. Lach, W. H. Mangione-smith, and M. Potkonjak, Robust FPGA intellectual property protection through multiple small watermarks, 36 th Design Automation Conference, 1999.

A. K. Jain, L. Yuan, P. R. Pari, and G. Qu, Zero overhead watermarking technique for FPGA designs', 13th Great Lakes symposium on VLSI, pp.147-152, 2003.

D. Ziener and J. Teich, Power Signature Watermarking of IP Cores for FPGAs, Journal of Signal Processing Systems, vol.51, issue.1, pp.51-123, 2008.
DOI : 10.1007/s11265-007-0136-8

M. Kasper, A. Moradi, and G. T. Becker, Side channels as building blocks, Journal of Cryptographic Engineering, vol.51, issue.1, pp.143-159, 2012.
DOI : 10.1007/s13389-012-0040-4

C. Marchand and L. Bossuet, IP watermark verification based on power consumption analysis, 2014 27th IEEE International System-on-Chip Conference (SOCC), 2014.
DOI : 10.1109/SOCC.2014.6948949
URL : https://hal.archives-ouvertes.fr/ujm-01063085

C. Marsh, T. Kean, and D. Mclaren, Protecting designs with a passive thermal tag, 2008 15th IEEE International Conference on Electronics, Circuits and Systems, pp.218-221, 2008.
DOI : 10.1109/ICECS.2008.4674830

R. Moudgil, D. Ganta, L. Nazhandali, M. Hsiao, C. Wang et al., A novel statistical and circuit-based technique for counterfeit detection in existing ICs', 23rd Great Lakes symposium on VLSI, pp.1-6, 2013.

R. Moudgil, A novel statistical and circuit-based technique for counterfeit detection in existing ICs, Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, GLSVLSI '13, 2013.
DOI : 10.1145/2483028.2483049

K. Huang, J. M. Carulli, and Y. Makris, Counterfeit electronics: A rising threat in the semiconductor manufacturing industry, 2013 IEEE International Test Conference (ITC), pp.1-4, 2013.
DOI : 10.1109/TEST.2013.6651880

F. Durvaux, B. Gerard, S. Kerckhof, F. Koeune, and F. X. Standaert, Intellectual Property Protection for Integrated Systems Using Soft Physical Hash Functions, pp.2012-208
DOI : 10.1007/978-3-642-35416-8_15

S. Kerckhof, F. Durvaux, F. X. Standaert, and B. Gerard, Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results', IEEE International Workshop on Hardware- Oriented Security and Trust, pp.7-12, 2013.

S. Devadas, E. Suh, S. Paral, R. Sowell, T. Ziola et al., Design and implementation of PUFbased "unclonable" RFID ICs for anti-counterfeiting and security applications, IEEE International Conference on RFID, pp.58-64, 2008.

A. Maiti, J. Casarona, L. Mchale, and P. Schaumont, A large scale characterization of RO-PUF, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.94-99, 2010.
DOI : 10.1109/HST.2010.5513108

S. Katzenbeisser, U. Kocabas, V. Rozic, A. R. Sadeghi, I. Verbauwhede et al., PUFs: Myth, Fact or Busted? A Security Evaluation of Physically Unclonable Functions??(PUFs) Cast in Silicon, Workshop on Cryptographic Hardware and Embedded Systems, pp.283-301, 2012.
DOI : 10.1007/978-3-642-33027-8_17

J. Guajardo, S. S. Kumar, G. J. Schrijen, and P. Tuyls, FPGA Intrinsic PUFs and Their Use for IP Protection, Workshop on Cryptographic Hardware and Embedded Systems, p.63, 2007.
DOI : 10.1007/978-3-540-74735-2_5

L. Bossuet, X. Ngo, Z. Cherif, and V. Fischer, A PUF Based on a Transient Effect Ring Oscillator and Insensitive to Locking Phenomenon, IEEE Transactions on Emerging Topics in Computing, vol.2, issue.1, pp.30-36, 2013.
DOI : 10.1109/TETC.2013.2287182
URL : https://hal.archives-ouvertes.fr/hal-00961503

S. S. Kumar, J. Guajardo, R. Maes, G. J. Schrijen, and P. Tuyls, The butterfly PUF protecting IP on every FPGA', IEEE International Workshop on Hardware-Oriented Security and Trust, pp.67-70, 2008.

Z. Cherif, J. L. Danger, S. Guilley, and L. Bossuet, An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF, 2012 15th Euromicro Conference on Digital System Design, pp.156-162, 2012.
DOI : 10.1109/DSD.2012.22
URL : https://hal.archives-ouvertes.fr/hal-00753216

S. Wei, F. Koushanfar, and M. Potkojnak, Integrated circuit digital rights management techniques using physical level characterization', 11th annual ACM workshop on Digital rights management, pp.3-14, 2011.

T. Kean, Cryptographic rights management of FPGA intellectual property cores, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays , FPGA '02, pp.113-118, 2002.
DOI : 10.1145/503048.503065

B. Soudan, W. Adi, and A. Hanoun, Novel secret-key IPR protection in FPGA environment, 2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics, pp.267-270, 2005.
DOI : 10.1109/SOCC.2005.1554508

R. Maes, D. Schellekens, and I. Verbauwhede, A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs, IEEE Transactions on Information Forensics and Security, vol.7, issue.1, pp.98-108, 2012.
DOI : 10.1109/TIFS.2011.2169667

T. Guneysu, B. Moller, and C. Paar, Dynamic Intellectual Property Protection for Reconfigurable Devices, 2007 International Conference on Field-Programmable Technology, pp.169-176, 2007.
DOI : 10.1109/FPT.2007.4439246

E. Simpson and P. Schaumont, Offline Hardware/Software Authentication for Reconfigurable Platforms, International Workshop on Cryptographic Hardware and Embedded Systems, pp.311-323, 2006.
DOI : 10.1007/11894063_25

J. Guajardo, T. Guneysu, S. S. Kumar, and C. Paar, Secure IP-block distribution for hardware devices', IEEE International Workshop on Hardware-Oriented Security and Trust, pp.82-89, 2009.

N. Couture and K. B. Kent, Periodic licensing of FPGA based intellectual property, Proceedings of the internation symposium on Field programmable gate arrays , FPGA'06, pp.357-360, 2006.
DOI : 10.1145/1117201.1117259

L. Parrilla, E. Castillo, A. Garcia, E. Todorovich, D. Gonzalez et al., Intellectual property protection of µP cores', Design of Circuits and Integrated Systems, 2009.

S. Narasimhan, R. S. Chakraborty, and S. Bhunia, Hardware IP protection during evaluation using embedded sequential trojan, IEEE Design & Test of Computers, issue.3, pp.29-70, 2012.

L. Bossuet and D. Hely, Salutary Hardware to design Trusted IC, Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00961641