Centrality Indicators for Efficient and Scalable Logic Masking

Abstract : Modifying the logic at register transfer level can help to protect a circuit against counterfeiting or illegal copying. By adding extra gates, the outputs can be controllably corrupted. Then the circuit operates correctly only if the right value is applied to the extra gates. The main challenge is to select the best position for these gates, to alter the circuit's behaviour as much as possible. However, another major point is the computational efficiency of the selection process, which should be as good as possible for integration in EDA tools. State-of-the art methods, based on fault analysis, are very demanding and cannot cope with large netlists in a reasonable runtime. We propose to use centrality indicators instead. Centrality is used to identify the most significant vertices of a graph. We show that, when used to select the nodes to modify, they lead to low correlation between original and altered outputs while being computationally efficient. We give experimental results on combinational benchmarks and compare to other previously proposed heuristics. We show that this method is the only efficient selection heuristic which is able to handle large netlists and integrate smoothly into EDA tools.
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Communication dans un congrès
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Jul 2017, Bochum, Germany. 2017 IEEE Computer Society Annual Symposium on VLSI, pp.98-103, 2017, 〈10.1109/ISVLSI.2017.26〉
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Brice Colombier, Lilian Bossuet, David Hely. Centrality Indicators for Efficient and Scalable Logic Masking. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Jul 2017, Bochum, Germany. 2017 IEEE Computer Society Annual Symposium on VLSI, pp.98-103, 2017, 〈10.1109/ISVLSI.2017.26〉. 〈ujm-01570080〉

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