A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

Abstract : This paper focused on a filter bank study used for ADC BIST. Filter selection to separate spectral components of an analog-to-digital converted signal are discussed. Regarding the BIST context, a method to realize the lowest cost filter bank is proposed. This task has been done taking into account the wordlenght of the input and clock frequencies and the filter coefficient values.
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Conference papers
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https://hal-ujm.archives-ouvertes.fr/ujm-00552169
Contributor : Lilian Bossuet <>
Submitted on : Wednesday, January 5, 2011 - 4:05:17 PM
Last modification on : Wednesday, July 25, 2018 - 2:05:31 PM

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  • HAL Id : ujm-00552169, version 1

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Nicolas Mechouk, Dominique Dallet, Lilian Bossuet, Bertrand Le Gal. A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing. IEEE International Conference on Electronics, Circuits and Systems, ICECS 2010, Dec 2010, Athens, Greece. pp.724-727. ⟨ujm-00552169⟩

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