A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

Nicolas Mechouk 1 Dominique Dallet 1 Lilian Bossuet 2, * Bertrand Le Gal 1
* Auteur correspondant
1 IMS - Laboratoire de l'intégration, du matériau au système
2 LHC - Laboratoire Hubert Curien [Saint Etienne]
Abstract : This paper focused on a filter bank study used for ADC BIST. Filter selection to separate spectral components of an analog-to-digital converted signal are discussed. Regarding the BIST context, a method to realize the lowest cost filter bank is proposed. This task has been done taking into account the wordlenght of the input and clock frequencies and the filter coefficient values.
Type de document :
Communication dans un congrès
IEEE International Conference on Electronics, Circuits and Systems, ICECS 2010, Dec 2010, Athens, Greece. pp.724-727, 2010
Liste complète des métadonnées
https://hal-ujm.archives-ouvertes.fr/ujm-00552169
Contributeur : Lilian Bossuet <>
Soumis le : mercredi 5 janvier 2011 - 16:05:17
Dernière modification le : mercredi 25 juillet 2018 - 14:05:31

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  • HAL Id : ujm-00552169, version 1

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UNIV-ST-ETIENNE | IMS-BORDEAUX | LAHC | IMS-BORDEAUX-FUSION | IOGS | PARISTECH

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Nicolas Mechouk, Dominique Dallet, Lilian Bossuet, Bertrand Le Gal. A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing. IEEE International Conference on Electronics, Circuits and Systems, ICECS 2010, Dec 2010, Athens, Greece. pp.724-727, 2010. 〈ujm-00552169〉

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