A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

Nicolas Mechouk; Dominique Dallet; Lilian Bossuet; Bertrand Le Gal

A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

Nicolas Mechouk ¹ Dominique Dallet ¹ Lilian Bossuet ^{2, *} Bertrand Le Gal ¹

* Corresponding author

1 IMS - Laboratoire de l'intégration, du matériau au système

2 LHC - Laboratoire Hubert Curien [Saint Etienne]

Abstract : This paper focused on a filter bank study used for ADC BIST. Filter selection to separate spectral components of an analog-to-digital converted signal are discussed. Regarding the BIST context, a method to realize the lowest cost filter bank is proposed. This task has been done taking into account the wordlenght of the input and clock frequencies and the filter coefficient values.

Document type :

Conference papers

Domain :

Computer Science [cs] / Embedded Systems

Complete list of metadatas

https://hal-ujm.archives-ouvertes.fr/ujm-00552169
Contributor : Lilian Bossuet <>
Submitted on : Wednesday, January 5, 2011 - 4:05:17 PM
Last modification on : Wednesday, July 25, 2018 - 2:05:31 PM

A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

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A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

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