Evaluation of Delays PUFs on CMOS 65 nm Technology: ASIC vs FPGA

Zouha Cherif (1, 2) , Jean-Luc Danger (2) , Lilian Bossuet (1)

1 LHC - Laboratoire Hubert Curien
2 Télécom ParisTech

This paper presents a work in progress on the comparison between the performance of two types of Physically Unclonable Functions (PUFs), namely the arbiter and the loop PUFs. The arbiter and the loop PUF are designed on two CMOS-65nm technology platforms: ASIC and FPGA (Xilinx Virtex-5). A mixed PUF design is proposed to allow a fair comparison between the two structures. The principal of the mixed PUF design consists on the use of the same delay chains on both arbiter and loop PUF structures. The comparison analysis reveals that the arbiter PUF structure has the worst performance when compared to the loop PUF, on both platforms. We also observe that the performance for both structures are better when designed on ASIC.

Mots clés: PUF; randomness; steadiness; uniqueness; FPGA; ASIC.; ASIC

Domaines: Systèmes embarqués; Cryptographie et sécurité [cs.CR]

Zouha Cherif, Jean-Luc Danger, Lilian Bossuet. Evaluation of Delays PUFs on CMOS 65 nm Technology: ASIC vs FPGA. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, TRUDEVICE 2013, May 2013, Avignon, France. ⟨ujm-00833893⟩