Correlation Analysis of the Power Consumption applied to IP watermark verification.

Abstract : The increasing production costs of electronic devices and changes in the design methods of integrated circuits (ICs) has led to emerging threats in the microelectronics industry. Intellectual property (IP) protection has become a major concern and we propose to fight counterfeiting and theft by designing salutary hardware (salware). A salware add protection by using the same means and strategies as malwares. One of the most studied salware is IP watermarking and many works propose to target the finite state machine of digital IP to perform the watermarking. But, most of the time, the verification of the watermark is not clearly described. This paper proposes a watermark verification scheme using a correlation analysis based on the measurement of the IC power consumption.
Type de document :
Communication dans un congrès
Colloque national du GDR SOC-SIP, Jun 2014, Paris, France
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https://hal-ujm.archives-ouvertes.fr/ujm-01015290
Contributeur : Nathalie Bochard <>
Soumis le : jeudi 26 juin 2014 - 11:02:39
Dernière modification le : jeudi 11 janvier 2018 - 06:20:35

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  • HAL Id : ujm-01015290, version 1

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Cédric Marchand, Lilian Bossuet. Correlation Analysis of the Power Consumption applied to IP watermark verification.. Colloque national du GDR SOC-SIP, Jun 2014, Paris, France. 〈ujm-01015290〉

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